Transformer Networks Enable Nanoscale Defect Detection at Advanced Semiconductor Nodes

Abstract

The relentless scaling of semiconductor manufacturing toward sub-5nm process nodes has rendered traditional optical and rule-based inspection systems increasingly inadequate for detecting nanoscale structural anomalies. This paper proposes a transformer-based deep learning framework for automated nanoscale defect detection in advanced semiconductor fabrication environments. The proposed architecture leverages self-attention mechanisms and multi-head feature extraction to capture long-range spatial dependencies across scanning electron microscopy (SEM) images of wafer surfaces, enabling high-sensitivity identification of defects including voids, bridging, line-edge roughness, and particle contamination. A hybrid pipeline combining a convolutional feature extractor with a Vision Transformer (ViT) encoder is developed and evaluated on a multi-class wafer defect dataset. Experimental results demonstrate that the proposed model achieves a defect detection accuracy of 97.3%, a false negative rate of 1.8%, and a mean average precision of 95.6%, outperforming conventional convolutional neural network (CNN)-based and support vector machine (SVM)-based baselines. The findings confirm that transformer architectures offer a compelling pathway for scalable, high-throughput semiconductor quality control, particularly as device geometries continue to shrink toward physical limits.